LogicVision Teams With Atrenta to Address Embedded Test Compliance in RTL
RTL Checking Can Save Up To Months of Re-Design
SAN JOSE, Calif.--(BUSINESS WIRE)--Dec. 5, 2001--LogicVision, Inc.
(Nasdaq:LGVN - news), a leading provider of embedded test solutions, and
Atrenta Inc., provider of SpyGlass(TM) rule checker for correct and
efficient design of electronic products, today announced that they are
partnering to address LogicVision's embedded test insertion
requirements early in the semiconductor's design cycle. The common
goals are to shave time off project schedules and improve the standard
Register Transfer Language (RTL) quality by providing a solution that
includes predictable logic states, the proper RTL subset for both test
and synthesis and increased observability of test nodes. LogicVision
has chosen Atrenta as a strategic partner because of the advanced
rule-checking capability of SpyGlass. Atrenta's fast-synthesis engine
allows for true structural-level analysis thus enabling test
requirements to be validated as early as the RTL stage. By checking
the RT-level code early in the design process, LogicVision and Atrenta
expect to help designers save weeks or even months of re-coding,
re-synthesis and re-verification encountered when rule violations are
not found until late in the design cycle during test insertion.
"Partnering with Atrenta is critical in providing our customers a
capability to improve the predictability of embedded test insertion at
the beginning of the design phase, helping to shorten electronic
product development cycles," stated Dr. Vinod K. Agarwal, president
and CEO of LogicVision. "The RTL rules sign-off is a necessary
pre-requisite to any viable RTL-to-GDSII flow."
LogicVision and Atrenta will work together to develop
sophisticated rules designed to catch complex problems responsible for
bus contention, clocking violations, undesirable state changes and
much more. By solving problems at the RT-level, designers will be
another step closer to having sign-off quality RTL code.
"LogicVision's proven embedded test technologies are becoming even
more important as design complexity increases," stated Dr. Ajoy Bose,
chairman, president and CEO of Atrenta. "By working together, we will
enable ASIC and SoC designers to develop RTL that is fully compliant
with LogicVision's embedded test flow and automation software,
significantly reducing the time required for subsequent embedded test
implementation. This will help bridge the gap between design engineers
and test engineers."
About LogicVision
LogicVision (Nasdaq:LGVN - news) provides proprietary technologies for
embedded test that enable the more efficient design and manufacture of
complex semiconductors. LogicVision's embedded test solution allows
integrated circuit designers to embed into a semiconductor design test
functionality that can be used during semiconductor production and
throughout the useful life of the chip. For more information on the
company and its products, please visit the LogicVision website at
www.logicvision.com.
About Atrenta
Atrenta's breakthrough SpyGlass rule checker captures, aggregates,
distributes and applies collective knowledge and constraints critical
for correct and efficient design of electronic products. Atrenta's
customers, such as Agilent, Apple, ARM, Canon, Compaq, Hitachi, LSI
Logic, Motorola, National Semiconductor and NCR, are using SpyGlass to
achieve shorter overall design cycles, increased design productivity
and lower costs. Atrenta, a spin-off of Interra, Inc., is
headquartered in San Jose, California, with European headquarters in
Swindon, England, and a sales and support distributor in Japan. For
further information, visit the Atrenta website at www.atrenta.com or
call 1-866-ATRENTA.
FORWARD LOOKING STATEMENTS:
Except for the historical information contained herein, the
matters set forth in this press release, including statements as to
the expected benefits of the strategic partnership, are
forward-looking statements within the meaning of the Private
Securities Litigation Reform Act of 1995. These forward-looking
statements are subject to risks and uncertainties that could cause
actual results to differ materially, including, but not limited to,
the impact of competitive products and pricing and of alternative
technological advances, and other risks detailed in LogicVision's
Prospectus dated October 31, 2001 filed with the SEC and from time to
time in LogicVision's SEC reports. These forward-looking statements
speak only as of the date hereof. LogicVision disclaims any obligation
to update these forward-looking statements.LogicVision, Embedded Test,
LogicVision Ready and LogicVision logos are trademarks or registered
trademarks of LogicVision Inc. in the United States and other
countries. All other trademarks and service marks are the property of
their respective owners.
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ACRONYMS AND DEFINITIONS:
ATE: Automatic Test Equipment
ATPG: Automatic Test Pattern Generation
BIST: Built-in-Self-Test
DFT: Design-for-Test
EDA: Electronic Design Automation
GDSII: An industry format describing the physical structure of
the chip design and used to create mask tooling for chip
manufacturing.
GUI: Graphics User Interface
HDL: Hardware Description Language -- Describes the
architecture and behavior of discrete electronic systems.
IC: Integrated Circuit
RTL: Register Transfer-Level -- A chip design language format
that is technology independent that can be Verilog or
VHDL.
Verilog: A hardware description language used to design and
document electronic systems. Verilog HDL.
VHDL: VHSIC (Very High-Speed Integrated Circuit) HDL
IP: Intellectual Property
SoC: System-on-chip
Contact:
LogicVision, Inc.
Clarisse Balistreri, 408/453-0146
clarisse@logicvision.com
OR
Atrenta
Mona Singh, 408/467-4248
mona@atrenta.com
OR
The Loomis Group (for LogicVision)
Vincent Mayeda, 909/614-1767
vincent@loomisgroup.com
OR
New Ideas in Communication (for Atrenta)
Paula Jones, 650/967-3711
paula@newiic.com
